VHDL语言IF语句问题

完整程轿缺脊序在下面：
把else if 改成elsif
elsif后面跟的条件语句应该也不对
添加几个程序包闭渗
A&B溢出了
只有bit变量支持移位运算

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
ENTITY ALU IS
PORT(S0,S1,S2,Cin:IN STD_LOGIC;
A,B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Cout:OUT STD_LOGIC;
F:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ALU;
ARCHITECTURE one OF ALU IS
signal s:std_logic_vector(2 downto 0);
BEGIN
s<=S0&S1&S2;
PROCESS(A,B,s,Cin)
BEGIN
IF(s="000")THEN F<扮配="00000000";
--ELSIF(s="001")THEN F<=A&B;
ELSIF(s="010")THEN F<=A OR B;
ELSIF(s="011")THEN F<=A XOR B;
ELSIF(s="100")THEN F<=A+B+Cin;
ELSIF(s="101")THEN F<=A+A;
ELSIF(s="110")THEN F <= to_stdlogicvector(to_bitvector(A) srl 1);
END IF;
END PROCESS;
END one;