问个简单的关于VHDL语言的问题

2024-12-05 00:13:41
推荐回答(2个)
回答(1):

library ieee;
use ieee.std_logic_1164.all;
entity kzq is
port(a,b:in std_logic;
c:out std_logic);
end entity;
architecture art of kzq is
begin
process(a,b)
begin
if a'event and a='1' then
c<='0';
else c<=b;
end if;
end process;
end art;

回答(2):

http://wenwen.soso.com/z/q125619011.htm?w=vhdl%D3%EF%D1%D4%BD%CC%B3%CC&spi=1&sr=4&w8=vhdl%E8%AF%AD%E8%A8%80%E6%95%99%E7%A8%8B&qf=20&rn=265&qs=4&ch=w.search.4
楼主看看这个例子