vhdl的编译和仿真出现这种问题怎么办

你设计了4个结构体，但每个结构体却只对一个输出端口赋值。这在编译时不会出现问题，却在综合的时候，综合器只默认综合最后一个结构体，前三个结构体没有被综合。
你应当将上述4个结构体整合成为一个结构体：
architecture hu of doc is
begin
led1<="11111110" when A="000"else
"1001110" when A="001"else
"1000111" when A="010"else
"1000111" when A="011"else
"0110111" when A="100"else
"0110111" when A="101"else
"0110111" when A="110"else
"0110111";
led2<="1111110" when A="000"else

"0011101" when A="001"else
"0011101" when A="010"else
"0011101" when A="011"else
"1001111" when A="100"else
"1001111" when A="101"else
"1001111" when A="110"else
"1001111";
led3<="1111110" when A="000"else

"0110000" when A="001"else
"0011101" when A="010"else
"0011101" when A="011"else
"0001110" when A="100"else
"0001110" when A="101"else
"0001110" when A="110"else
"0001110";
led4<="1111110" when A="000"else

"0111101" when A="001"else
"0111101" when A="010"else
"0111101" when A="011"else
"1100111" when A="100"else
"1100111" when A="101"else
"1100111" when A="110"else
"1100111";
end hu;