用VHDL设计一个异步置数，同步清零，计数使能和进位输出信号的16位二进制加法计数器

我写了一个，k是控制置数的，en是计数使能，clr是清零，下面附上了我的仿真波形图。
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity cnt_16 is
port (
clk: in STD_LOGIC;
qin: in STD_LOGIC_VECTOR (15 downto 0);
clr:in std_logic;
k: in std_logic;
en: in STD_LOGIC;
qout: out STD_LOGIC_VECTOR (15 downto 0);
q: out STD_LOGIC
);
end cnt_16;

architecture cnt_16_arch of cnt_16 is
signal qqout:std_logic_vector(15 downto 0);
signal qq:std_logic;

begin
process(k,qin,en,clk,clr)
begin
if k='1' then
qqout<=qin;
else
if clk'event and clk='1' then
if clr='1' then
qqout<="0000000000000000";
elsif en='1' then
if qqout="1111111111111111" then
qq<='1' ;
qqout<="0000000000000000";
else
qqout<=qqout+'1';
end if;
end if;
end if;
end if;

end process;

suocun: process(qqout,qq)
begin
q<=qq;
qout<=qqout;
end process suocun;

end cnt_16_arch;