verilog中寄存器信号能不能作为always语句的敏感信号

2024-11-05 11:55:16
推荐回答(1个)
回答(1):

可以,举个例子,三段式状态机中的第二段 就是将寄存器信号作为always语句的敏感信号!

reg [3:0] current_state ;
reg [3:0] next_state;

always @ (posedge clk or negedge rst_n)
if (!RSTn) current_state <= IDLE;
else current_state <= next_state;

always @ (current_state) //这里就是将寄存器信号作为always语句的敏感信号
begin
next_state = x;
case(current_state)
S1: if(...) next_state = S2;

....................

纯手打,望采纳,欢迎追问~~~~