编写上升沿触发的D触发器的VHDL语言程序

2024-12-04 09:07:20
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entity D_FF is

port
(
cp : in bit;
D : in bit;
Q : out bit
);
end D_FF;

architecture one of D_FF is

begin
process(cp)
begin
if(cp'event and cp='1') then
Q<=D;
end if;
end process;
end one;