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58问答库 > 用verilog编写一个编码译码器，用0-9 10个开关表示输入，并用数码管显示，求大神，明天不

用verilog编写一个编码译码器，用0-9 10个开关表示输入，并用数码管显示，求大神，明天不

2025-04-08 09:10:08

推荐回答（1个）

回答（1）：

module segment8( input [3:0] segin, output reg [7:0] segout); always @(seg_in) case(seg_in) //gfedcba 共阳极 4'b0000:segout=7'b1000000;//display digital 0(40H) 4'b0001:segout=7'b1111001;//display digital 1(79H) 4'b0010:segout=7'b0100100;//display digital 2(24H) 4'b0011:segout=7'b0110000;//display digital 3(30H) 4'b0100:segout=7'b0011001;//display digital 4(19H) 4'b0101:segout=7'b0010010;//display digital 5(12H) 4'b0110:segout=7'b0000010;//display digital 6(02H) 4'b0111:segout=7'b1111000;//display digital 7(78H) 4'b1000:segout=7'b0000000;//display digital 8(00H) 4'b1001:segout=7'b0010000;//display digital 9(10H) 4'b1010:segout=7'b0001000;//display digital A(08H) 4'b1011:segout=7'b0000011;//display digital B(03H) 4'b1100:segout=7'b0100111;//display digital C(27H) 4'b1101:segout=7'b1000001;//display digital d(21H) 4'b1110:segout=7'b0000110;//display digital E(06H) 4'b1111:segout=7'b0001110;//display digital F(0EH) default:segout=7'b0100011;//display digital 0(23H) endcase endmodule

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