以真值表为依据,用vhdl描述2输入或非门

2025-03-22 03:17:56
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ENTITY or_not IS
PORT(in_1,in_2:IN bit;out_0:OUT bit);
END or_not;
architecture one of or_not is
begin
out_0 <= '1' when (in_1 OR in_2 ='0') else
'0';
end one;