58问答库 > 请用MAX+PLUS II软件的文本（VHDL）输入法设计如下电路

请用MAX+PLUS II软件的文本（VHDL）输入法设计如下电路

2025-03-07 01:15:03

推荐回答（2个）

回答（1）：

我些个代码在这，其中第四个我不会写，其他4个我都仿真了，用的是XIlinx仿真的。很辛苦的……呵呵。

第一个：library IEEE;
use IEEE.std_logic_1164.all;

entity yima is
port (
din: in STD_LOGIC_VECTOR (3 downto 0);
dout: out STD_LOGIC_VECTOR (15 downto 0)
);
end yima;

architecture yima_arch of yima is
begin
process(din)
begin
case din is
when "0000"=>dout<="1111111111111110";
when "0001"=>dout<="1111111111111101";
when "0010"=>dout<="1111111111111011";
when "0011"=>dout<="1111111111110111";
when "0100"=>dout<="1111111111101111";
when "0101"=>dout<="1111111111011111";
when "0110"=>dout<="1111111110111111";
when "0111"=>dout<="1111111101111111";
when "1000"=>dout<="1111111011111111";
when "1001"=>dout<="1111110111111111";
when "1010"=>dout<="1111101111111111";
when "1011"=>dout<="1111011111111111";
when "1100"=>dout<="1110111111111111";
when "1101"=>dout<="1101111111111111";
when "1110"=>dout<="1011111111111111";
when "1111"=>dout<="0111111111111111";
when others=>dout<="ZZZZZZZZZZZZZZZZ";
end case;
end process;
end yima_arch;

第二个：
library IEEE;
use IEEE.std_logic_1164.all;

entity bianma is
port (
din: in STD_LOGIC_VECTOR (15 downto 0);
dout: out STD_LOGIC_VECTOR (3 downto 0)
);
end bianma;

architecture bianma_arch of bianma is
begin
process(din)
begin
if din="1111111111111110" then dout<="0000";
elsif din="1111111111111101" then dout<="0001";
elsif din="1111111111111011" then dout<="0010";
elsif din="1111111111110111" then dout<="0011";
elsif din="1111111111101111" then dout<="0100";
elsif din="1111111111011111" then dout<="0101";
elsif din="1111111110111111" then dout<="0110";
elsif din="1111111101111111" then dout<="0111";
elsif din="1111111011111111" then dout<="1000";
elsif din="1111110111111111" then dout<="1001";
elsif din="1111101111111111" then dout<="1010";
elsif din="1111011111111111" then dout<="1011";
elsif din="1110111111111111" then dout<="1100";
elsif din="1101111111111111" then dout<="1101";
elsif din="1011111111111111" then dout<="1110";
elsif din="0111111111111111" then dout<="1111";
else
dout<="ZZZZ";
end if;
end process;
end bianma_arch;

第三个：
library IEEE;
use IEEE.std_logic_1164.all;

entity shuxuan is
port (
din: in STD_LOGIC_VECTOR (15 downto 0);
com: in STD_LOGIC_VECTOR (3 downto 0);
qout: out STD_LOGIC
);
end shuxuan;

architecture shuxuan_arch of shuxuan is
begin

qout<=din(0) when com="0000" else
din(1) when com="0001" else
din(2) when com="0010" else
din(3) when com="0011" else
din(4) when com="0100" else
din(5) when com="0101" else
din(6) when com="0110" else
din(7) when com="0111" else
din(8) when com="1000" else
din(9) when com="1001" else
din(10) when com="1010" else
din(11) when com="1011" else
din(12) when com="1100" else
din(13) when com="1101" else
din(14) when com="1110" else
din(15) when com="1111" else
'Z';
end shuxuan_arch;

第五个：
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity jishu is
port (
clk: in STD_LOGIC;
s: in STD_LOGIC;
cnt: buffer STD_LOGIC_VECTOR (3 downto 0)
);
end jishu;

architecture jishu_arch of jishu is
begin
process(clk)
begin
if clk'event and clk='1' then
if s='1' then
if cnt="1111" then cnt<="0000";
else cnt<= cnt+'1';
end if;
else
if cnt="0000" then cnt<="1111";
else cnt<=cnt-'1';
end if;
end if;
end if;
end process;
end jishu_arch;

最后一个：

library IEEE;
use IEEE.std_logic_1164.all;

entity jiance is
port (
din: in STD_LOGIC;
clk: in STD_LOGIC;
clr: in STD_LOGIC;
qout: out STD_LOGIC
);
end jiance;

architecture jiance_arch of jiance is
signal q:integer range 0 to 7;
signal d:std_logic_vector ( 6 downto 0);
begin
d<="1110010";
process(clk,clr)
begin
if clr='1' then q<=0;
elsif clk'event and clk='1'then
case q is
when 0=> if din=d(6) then q<=1;else q<=0;end if;
when 1=> if din=d(5) then q<=2;else q<=0;end if;
when 2=> if din=d(4) then q<=3;else q<=0;end if;
when 3=> if din=d(3) then q<=4;else q<=0;end if;
when 4=> if din=d(2) then q<=5;else q<=0;end if;
when 5=> if din=d(1) then q<=6;else q<=0;end if;
when 6=> if din=d(0) then q<=7;else q<=0;end if;
when others =>q<=0;
end case;
end if;
end process;
process(q)
begin
if q=7 then qout<='1';
else qout<='0';
end if;
end process;
end jiance_arch;

回答（2）：

.b,bn,,,

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