用VHDL编写一个分频器,实现输出1MHz-1Hz之间的任意频率

clk 输入一个相对较大的频率,
频率哪腊要多少就用N_diviseur除!

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;

ENTITY div IS
GENERIC( n_diviseur : INTEGER := 2 );
PORT ( clk : IN Std_Logic;
clock : OUT Std_Logic);
END ENTITY;

ARCHITECTURE beha OF div IS
BEGIN
PROCESS (clk)
VARIABLE compteur : INTEGER RANGE 0 TO n_diviseur;

BEGIN

IF (clk'EVENT AND clk = '1') THEN
IF (compteur >= n_diviseur-1) THEN
compteur := 0;
clock <= '1'码缓携迟伏;
ELSE
compteur := compteur + 1;
clock <= '0';
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;

library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity div_ry is
port(
clk_in :in std_logic;---------input clk
d:in std_logic_vector(7 downto 0);----------分频系数，根据你实际频率算下，用拨历雹告码开关实现
clk_out :out std_logic);-------输肆胡出clk
end div_ry;

architecture behav of div_ry is
signal clk_reg :std_logic;
signal cnt :integer;
begin
process(clk_in)
begin
if clk_in'肢明event and clk_in='1' then
if cnt = d then
cnt<=0;
clk_reg<=not clk_reg;
else
cnt<=cnt+1;
end if;
end if;
clk_out<=clk_reg;
end process;
end behav;
能实现

控制分频比可以实现你的设计，达到
步进明兆渣=1HZ,
clkin=32MHz;
Jitter=1/16Ui.
简单原理就是你用分频器分出M分频猜洞和N分频的不同比重来实现激悄步进1Hz.