请教关于verilog HDL语言中关于always语句块的问题？

假设你要检测的信号是1bit的sign_in,代码如下
rising_edge拉高时代表检测到上升沿
falling_edge拉高时代表检测到下降沿
rising_edge || falling_edge 代表检测到边沿

reg[1:0] sign_in_d;
reg rising_edge;
reg falling_edge;

always@(posedge clk)
sign_in_d <= {sign_in_d[0],sign_in};

always@(posedge clk or negedge rstn)
if(rstn == 1'b0)
rising_edge <= 1'b0;
else if(sign_in_d == 2'b01)
rising_edge <= 1'b1;
else
rising_edge <= 1'b0;

always@(posedge clk or negedge rstn)
if(rstn == 1'b0)
falling_edge <= 1'b0;
else if(sign_in_d == 2'b10)
falling_edge <= 1'b1;
else
falling_edge <= 1'b0;

是的,这里的*号代替了本always模块里面所有的触发信号。